NAND type EEPROMs (Electrically Erasable Programmable Read Only Memories) or flash memories have been developed for solid-state mass storage applications for portable music players, mobile telephones, digital cameras, and the like, as well as have been considered as a replacement for hard disk drives (HDDs).
The narrow, long polysilicon word lines of the flash array have long RC delays associated therewith which must be considered when reading data from the array. Parasitic and word line to word line capacitances contribute to the RC delay, as a selected word line is initially coupled up to the higher voltage of adjacent deselected word lines, meaning accurate reading cannot occur until the selected word line dissipates the coupled voltage. Coupling becomes particularly strong between closely spaced word lines. Coupling between the select gate of the selected word line and the adjacent word line can also contribute to this delay in split gate flash cells, such as described in, for example, U.S. Pat. No. 6,291,297 to Chen (US '297), the entirety of which is hereby incorporated by reference herein.
As mentioned, these RC delays contribute to the total access time required to read data from flash memory cells. Typically, the access time is around 10 μs for memory cell densities below 512 Mb and around 25 μs for densities above 1 Gb. Although, conceptually at least, metal shunts can be used to reduce the RC delay, their use is generally not preferred because of the additional costs associated therewith and the difficulty in providing the shunt metal in such narrow pitches.
Therefore, there remains a need for an improved flash memory with improved reading times and method of reading data from a flash memory.